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1/33 march 2000 m29w800at M29W800AB 8 mbit (1mb x8 or 512kb x16, boot block) low voltage single supply flash memory n 2.7v to 3.6v supply voltage for program, erase and read operations n access time: 80ns n programming time: 10 m s typical n program/erase controller (p/e.c.) program byte-by-byte or word-by-word status register bits and ready/busy output n security protection memory area n instruction address coding: 3 digits n memory blocks boot block (top or bottom location) parameter and main blocks n block, multi-block and chip erase n multi block protection/temporary unprotection modes n erase suspend and resume modes read and program another block during erase suspend n low power consumption stand-by and automatic stand-by n 100,000 program/erase cycles per block n 20 years data retention defectivity below 1ppm/year n electronic signature manufacturer code: 20h top device code, m29w800at: d7h bottom device code, M29W800AB: 5bh figure 1. logic diagram ai02599 19 a0-a18 w dq0-dq14 v cc m29w800at M29W800AB e v ss 15 g rp dq15a1 byte rb 44 1 fbga tsop48 (n) 12 x 20mm so44 (m) lfbga48 (za) 8 x 6 solder balls
m29w800at, M29W800AB 2/33 figure 2. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15a1 v cc dq4 dq5 a7 dq7 nc nc ai02179 m29w800t m29w800b 12 1 13 24 25 36 37 48 dq8 nc nc a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss figure 3. so connections g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 w rb a4 rp a7 ai02181 m29w800 t m29w800b 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 a18 table 1. signal names a0-a18 address inputs dq0-dq7 data input/outputs, command inputs dq8-dq14 data input/outputs dq15a1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization v cc supply voltage v ss ground nc not connected internally du don't use as internally connected description the m29w800a is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a byte-by-byte or word-by-word basis using only a single 2.7v to 3.6v v cc supply. for program and erase opera- tions the necessary high voltages are generated internally. the device can also be programmed in standard programmers. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. blocks can be protected against pro- graming and erase on programming equipment, and temporarily unprotected to make changes in the application. each block can be programmed and erased over 100,000 cycles. instructions for read/reset, auto select for read- ing the electronic signature or block protection status, programming, block and chip erase, erase suspend and resume are written to the de- vice in cycles of commands to a command inter- face using standard microprocessor write timings. the device is offered in tsop48 (12 x 20mm), so44 and lfbga48 0.8 mm ball pitch packages.
3/33 m29w800at, M29W800AB figure 4. lfbga connections (top view through package) ai00656 d e f 8 7 6 5 4 3 2 1 b c a v ss dq15 a1 a15 a14 a12 a13 dq3 dq11 dq10 a18 du rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 du du rp w a11 dq7 a1 a2 v ss a5 du a16 byte memory blocks the devices feature asymmetrically blocked archi- tecture providing system memory integration. both m29w800at and M29W800AB devices have an array of 19 blocks, one boot block of 16 kbytes or 8 kwords, two parameter blocks of 8 kbytes or 4 kwords, one main block of 32 kbytes or 16 kwords and fifteen main blocks of 64 kbytes or 32 kwords. the m29w800at has the boot block at the top of the memory address space and the M29W800AB locates the boot block starting at the bottom. the memory maps are showed in figure 5. each block can be erased separately, any combi- nation of blocks can be specified for multi-block erase or the entire chip may be erased. the erase operations are managed automatically by the p/ e.c. the block erase operation can be suspended in order to read from or program to any block not being erased, and then resumed. block protection provides additional data security. each block can be separately protected or unpro- tected against program or erase on programming equipment. all previously protected blocks can be temporarily unprotected in the application. organisation the m29w800a is organised as 1m x8 or 512k x16 bits selectable by the byte signal. when byte is low the byte-wide x8 organisation is se- lected and the address lines are dq15a1 and a0-a18. the data input/output signal dq15a1 acts as address line a1 which selects the lower or upper byte of the memory word for output on dq0-dq7, dq8-dq14 remain at high impedance. when byte is high the memory uses the address inputs a0-a18 and the data input/outputs dq0- dq15. memory control is provided by chip enable e, output enable g and write enable w inputs. a reset/block temporary unprotection rp tri-lev- el input provides a hardware reset when pulled low, and when held high (at v id ) temporarily un- protects blocks previously protected allowing them to be programed and erased. erase and program operations are controlled by an internal program/ erase controller (p/e.c.). status register data output on dq7 provides a data polling signal, and dq6 and dq2 provide toggle signals to indicate the state of the p/e.c operations. a ready/busy rb output indicates the completion of the internal algorithms.
m29w800at, M29W800AB 4/33 bus operations the following operations can be performed using the appropriate bus cycles: read (array, electron- ic signature, block protection status), write com- mand, output disable, stan-by, reset, block protection, unprotection, protection verify, unpro- tection verify and block temporary unprotection. see tables 5 and 6. command interface instructions, made up of commands written in cy- cles, can be given to the program/erase controller through a command interface (c.i.). for added data protection, program or erase execution starts after 4 or 6 cycles. the first, second, fourth and fifth cycles are used to input coded cycles to the c.i. this coded sequence is the same for all pro- gram/erase controller instructions. the 'com- mand' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. any incorrect command or any improper command se- quence will reset the device to read array mode. instructions seven instructions are defined to perform read array, auto select (to read the electronic signa- ture or block protection status), program, block erase, chip erase, erase suspend and erase re- sume. the internal p/e.c. automatically handles all tim- ing and verification of the program and erase op- erations. the status register data polling, toggle, error bits and the rb output may be read at any time, during programming or erase, to mon- itor the progress of the operation. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all in- structions (see table 9). the third cycle inputs the instruction set-up com- mand. subsequent cycles output the addressed data, electronic signature or block protection sta- tus for read operations. in order to give additional data protection, the instructions for program and block or chip erase require further command in- puts. for a program instruction, the fourth com- mand cycle inputs the address and data to be programmed. for an erase instruction (block or chip), the fourth and fifth cycles input a further coded sequence before the erase confirm com- mand on the sixth cycle. erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. when power is first ap- plied or if v cc falls below v lko , the command in- terface is reset to read array. table 2. absolute maximum ratings (1) note: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns during transitions. 3. depends on range. symbol parameter value unit t a ambient operating temperature (3) 40 to 85 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltage 0.6 to 5 v v cc supply voltage 0.6 to 5 v v (a9, e, g, rp) (2) a9, e, g, rp voltage 0.6 to 13.5 v
5/33 m29w800at, M29W800AB table 3. top boot block addresses, m29w800at # size (kbytes) address range (x8) address range (x16) 18 16 fc000h-fffffh 7e000h-7ffffh 17 8 fa000h-fbfffh 7d000h-7dfffh 16 8 f8000h-f9fffh 7c000h-7cfffh 15 32 f0000h-f7fffh 78000h-7bfffh 14 64 e0000h-effffh 70000h-77fffh 13 64 d0000h-dffffh 68000h-6ffffh 12 64 c0000h-cffffh 60000h-67fffh 11 64 b0000h-bffffh 58000h-5ffffh 10 64 a0000h-affffh 50000h-57fffh 9 64 90000h-9ffffh 48000h-4ffffh 8 64 80000h-8ffffh 40000h-47fffh 7 64 70000h-7ffffh 38000h-3ffffh 6 64 60000h-6ffffh 30000h-37fffh 5 64 50000h-5ffffh 28000h-2ffffh 4 64 40000h-4ffffh 20000h-27fffh 3 64 30000h-3ffffh 18000h-1ffffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh table 4. bottom boot block addresses, M29W800AB # size (kbytes) address range (x8) address range (x16) 18 64 f0000h-fffffh 78000h-7ffffh 17 64 e0000h-effffh 70000h-77fffh 16 64 d0000h-dffffh 68000h-6ffffh 15 64 c0000h-cffffh 60000h-67fffh 14 64 b0000h-bffffh 58000h-5ffffh 13 64 a0000h-affffh 50000h-57fffh 12 64 90000h-9ffffh 48000h-4ffffh 11 64 80000h-8ffffh 40000h-47fffh 10 64 70000h-7ffffh 38000h-3ffffh 9 64 60000h-6ffffh 30000h-37fffh 8 64 50000h-5ffffh 28000h-2ffffh 7 64 40000h-4ffffh 20000h-27fffh 6 64 30000h-3ffffh 18000h-1ffffh 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffffh 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 00000h-03fffh 00000h-01fffh
m29w800at, M29W800AB 6/33 signal descriptions see figure 1 and table 1. address inputs (a0-a18). the address inputs for the memory array are latched during a write op- eration on the falling edge at chip enable e or write enable w. in word-wide organisation the address lines are a0-a18, in byte-wide organisa- tion dq15a1 acts as an additional lsb address line. when a9 is raised to v id , either a read elec- tronic signature manufacturer or device code, block protection status or a write block protection or block unprotection is enabled depending on the combination of levels on a0, a1, a6, a12 and a15. data input/outputs (dq0-dq7). these inputs/ outputs are used in the byte-wide and word-wide organisations. the input is data to be programmed in the memory array or a command to be written to the c.i. both are latched on the rising edge of chip enable e or write enable w. the output is data from the memory array, the electronic signature manufacturer or device codes, the block protec- tion status or the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when chip enable e and output enable g are ac- tive. the output is high impedance when the chip is deselected or the outputs are disabled and when rp is at a low level. data input/outputs (dq8-dq14 and dq15a 1). these inputs/outputs are additionally used in the word-wide organisation. when byte is high dq8-dq14 and dq15a1 act as the msb of the data input or output, functioning as described for dq0-dq7 above, and dq8-dq15 are 'don't care' for command inputs or status outputs. when byte is low, dq0-dq14 are high impedance, dq15a1 is the address a1 input. chip enable (e). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e high deselects the memory and reduces the power consumption to the stan-by level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at a low level. the chip enable must be forced to v id during the block un- protection operation. output enable (g). the output enable gates the outputs through the data buffers during a read op- eration. when g is high the outputs are high im- pedance. g must be forced to v id level during block protection and unprotection operations. write enable (w). this input controls writing to the command register and address and data latches. byte/word organization select (byte). the byte input selects the output configuration for the de- vice: byte-wide (x8) mode or word-wide (x16) mode. when byte is low, the byte-wide mode is selected and the data is read and programmed on dq0-dq7. in this mode, dq8-dq14 are at high impedance and dq15a1 is the lsb address. when byte is high, the word-wide mode is se- lected and the data is read and programmed on dq0-dq15. ready/busy output (rb). ready/busy is an open-drain output and gives the internal state of the p/e.c. of the device. when rb is low, the de- vice is busy with a program or erase operation and it will not accept any additional program or erase instructions except the erase suspend in- struction. when rb is high, the device is ready for any read, program or erase operation. the rb will also be high when the memory is put in erase suspend or stan-by modes. reset/block temporary unprotect input (rp). the rp input provides hardware reset and pro- tected block(s) temporary unprotection functions. reset of the memory is achieved by pulling rp to v il for at least t plpx . when the reset pulse is giv- en, if the memory is in read or stan-by modes, it will be available for new operations in t phel after the rising edge of rp. if the memory is in erase, erase suspend or program modes the reset will take t plyh during which the rb signal will be held at v il . the end of the memory reset will be indicat- ed by the rising edge of rb. a hardware reset dur- ing an erase or program operation will corrupt the data being programmed or the sector(s) being erased. see tables 15, 16, and figure 11. temporary block unprotection is made by holding rp at v id . in this condition previously protected blocks can be programmed or erased. the transi- tion of rp from v ih to v id must slower than t ph- phh . see tables 17, 18, and figure 11. when rp is returned from v id to v ih all blocks temporarily unprotected will be again protected. v cc supply voltage. the power supply for all operations (read, program and erase). v ss ground. v ss is the reference for all voltage measurements.
7/33 m29w800at, M29W800AB device operations see tables 5, 6 and 7. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register or the block protection status. both chip enable e and output enable g must be low in order to read the output of the mem- ory. a new operation is initiated either on the fol- lowing edge of chip enable e or on any address transition with e at v il . write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and input data are latched on the rising edge of w or e whichever oc- curs first. output disable. the data outputs are high im- pedance when the output enable g is high with write enable w high. stan-by. the memory is in stan-by when chip enable e is high and the p/e.c. is idle. the power consumption is reduced to the stan-by level and the outputs are high impedance, independent of the output enable g or write enable w inputs. automatic stan-by. after 150ns of bus inactivity (no address transition, ce = v il ) and when cmos levels are driving the addresses, the chip automat- ically enters a pseudo-stan-by mode where con- sumption is reduced to the cmos stan-by value, while outputs still drive the bus (if g = v il ). electronic signature. two codes identifying the manufacturer and the device can be read from the memory. the manufacturer's code for stmicro- electronics is 20h, the device code is d7h for the m29w800at (top boot) and 5bh for the M29W800AB (bottom boot). these codes allow programming equipment or applications to auto- matically match their interface to the characteris- tics of the m29w800a. the electronic signature is output by a read operation when the voltage ap- plied to a9 is at v id and address inputs a1 is low. the manufacturer code is output when the ad- dress input a0 is low and the device code when this input is high. other address inputs are ig- nored. the codes are output on dq0-dq7. the electronic signature can also be read, without raising a9 to v id , by giving the memory the in- struction as. if the byte-wide configuration is se- lected the codes are output on dq0-dq7 with dq8-dq14 at high impedance; if the word-wide configuration is selected the codes are output on dq0-dq7 with dq8-dq15 at 00h. block protection. each block can be separately protected against program or erase on program- ming equipment. block protection provides addi- tional data security, as it disables all program or erase operations. this mode is activated when both a9 and g are raised to v id and an address in the block is applied on a12-a18. block protection is initiated on the edge of w falling to v il . then af- ter a delay of 100 m s, the edge of w rising to v ih ends the protection operations. block protection verify is achieved by bringing g, e, a0 and a6 to v il and a1 to v ih , while w is at v ih and a9 at v id . under these conditions, reading the data output will yield 01h if the block defined by the inputs on a12-a18 is protected. any attempt to program or erase a protected block will be ignored by the de- vice. block temporary unprotection. any previously protected block can be temporarily unprotected in order to change stored data. the temporary un- protection mode is activated by bringing rp to v id . during the temporary unprotection mode the pre- viously protected blocks are unprotected. a block can be selected and data can be modified by exe- cuting the erase or program instruction with the rp signal held at v id . when rp is returned to v ih , all the previously protected blocks are again pro- tected. block unprotection. all protected blocks can be unprotected on programming equipment to allow updating of bit contents. all blocks must first be protected before the unprotection operation. block unprotection is activated when a9, g and e are at v id and a12, a15 at v ih . unprotection is initiated by the edge of w falling to v il . after a delay of 10ms, the unprotection operation will end. unpro- tection verify is achieved by bringing g and e to v il while a0 is at v il , a6 and a1 are at v ih and a9 remains at v id . in these conditions, reading the output data will yield 00h if the block defined by the inputs a12-a18 has been successfully unprotect- ed. each block must be separately verified by giv- ing its address in order to ensure that it has been unprotected.
m29w800at, M29W800AB 8/33 table 5. user bus operations (1) note: 1. x = v il or v ih . 2. block address must be given an a12-a18 bits. 3. see table 7. 4. operation performed on programming equipment. table 6. read electronic signature (following as instruction or with a9 = v id ) table 7. read block protection with as instruction operation e g w rp byte a0 a1 a6 a9 a12 a15 dq0- dq7 dq8- dq14 dq15 a1 read word v il v il v ih v ih v ih a0 a1 a6 a9 a12 a15 data output data output data output read byte v il v il v ih v ih v il a0 a1 a6 a9 a12 a15 data output hi-z address input write word v il v ih v il v ih v ih a0 a1 a6 a9 a12 a15 data input data input data input write byte v il v ih v il v ih v il a0 a1 a6 a9 a12 a15 data input hi-z address input output disable v il v ih v ih v ih x xxxx x x hi-z hi-z hi-z stan-by v ih xx v ih x xxxx x x hi-z hi-z hi-z reset x x x v il x xxxx x x hi-z hi-z hi-z block protection (2,4) v il v id v il pulse v ih x xxx v id xx x x x blocks unprotection (4) v id v id v il pulse v ih x xxx v id v ih v ih xxx block protection verify (2,4) v il v il v ih v ih x v il v ih v il v id a12 a15 block protect status (3) xx block unprotection verify (2,4) v il v il v ih v ih x v il v ih v ih v id a12 a15 block protect status (3) xx block temporary unprotection xx x v id x xxxx x x x x x org. code device e g w byte a0 a1 other addresses dq0- dq7 dq8- dq14 dq15 a1 word- wide manufact. code v il v il v ih v ih v il v il don't care 20h 00h 0 device code m29w800at v il v il v ih v ih v ih v il don't care d7h 00h 0 M29W800AB v il v il v ih v ih v ih v il don't care 5bh 00h 0 code e g w a0 a1 a12-a18 other addresses dq0-dq7 protected block v il v il v ih v il v ih block address don't care 01h unprotected block v il v il v ih v il v ih block address don't care 00h
9/33 m29w800at, M29W800AB table 8. commands hex code command 00h invalid/reserved 10h chip erase confirm 20h reserved 30h block erase resume/confirm 80h set-up erase 90h read electronic signature/ block protection status a0h program b0h erase suspend f0h read array/reset instructions and commands the command interface latches commands writ- ten to the memory. instructions are made up from one or more commands to perform read memory array, read electronic signature, read block pro- tection, program, block erase, chip erase, erase suspend and erase resume. commands are made of address and data sequences. the in- structions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. they are followed by either further write cycles to confirm the first command or execute the command immediately. command se- quencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. in- structions are initialised by two initial coded cycles which unlock the command interface. in addition, for erase, instruction confirmation is again preced- ed by the two coded cycles. status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 and erase timer dq3 bits. any read attempt during program or erase com- mand execution will automatically output these five status register bits. the p/e.c. automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked. see tables 10 and 11. data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a '0'. after com- pletion of the operation, dq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be per- formed at the address being programmed or at an address within the block being erased. if all the blocks selected for erasure are protected, dq7 will be set to '0' for about 100 m s, and then return to the previous addressed memory data value. see fig- ure 13 for the data polling flowchart and figure 12 for the data polling waveforms. dq7 will also flag the erase suspend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an ad- dress within a block being erased must be provid- ed. for a read operation in erase suspend mode, dq7 will output '1' if the read is attempted on a block being erased and the data value on oth- er blocks. during program operation in erase sus- pend mode, dq7 will have the same behavior as in the normal program execution outside of the suspend mode. toggle bit (dq6). when programming or eras- ing operations are in progress, successive at- tempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g, or e when g is low. the operation is completed when two successive reads yield the same output data. the next read will output the bit last pro- grammed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the blocks selected for erasure are protected, dq6 will toggle for about 100 m s and then return back to read. dq6 will be set to '1' if a read operation is attempted on an erase suspend block. when erase is suspended dq6 will toggle during programming operations in a block different to the block in erase suspend. ei- ther e or g toggling will cause dq6 to toggle. see figure 14 for toggle bit flowchart and figure 15 for toggle bit waveforms.
m29w800at, M29W800AB 10/33 table 9. instructions (1) note: 1. commands not interpreted in this table will default to read array mode. 2. a wait of t plyh is necessary after a read/reset command if the memory was in an erase or program mode before starting any new operation (see tables 15, 16 and figure 11). 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the com- mand cycles. 5. signature address bits a0, a1, at v il will output manufacturer code (20h). address bits a0 at v ih and a1, at v il will output device code. 6. block protection address: a0, at v il ,a1atv ih and a15-a18 within the block will output the block protection status. 7. for coded cycles address inputs a11-a18 are don't care. 8. optional, additional blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be verified through dq3 value (see erase timer bit dq3 description). when full command is entered, read data polli ng or toggle bit until erase is completed or suspended. 9. read data polling, toggle bits or rb until erase completes. 10. during erase suspend, read and data program functions are allowed in blocks not being erased. mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) byte aaah 555h aaah read memory array until a new write cycle is initiated. word 555h 2aah 555h data aah 55h f0h as (4) auto select 3+ addr. (3,7) byte aaah 555h aaah read electronic signature or block protection status until a new write cycle is initiated. see note 5 and 6. word 555h 2aah 555h data aah 55h 90h pg program 4 addr. (3,7) byte aaah 555h aaah program address read data polling or toggle bit until program completes. word 555h 2aah 555h data aah 55h a0h program data be block erase 6 addr. (3,7) byte aaah 555h aaah aaah 555h block address additional block (8) word 555h 2aah 555h 555h 2aah data aah 55h 80h aah 55h 30h 30h ce chip erase 6 addr. (3,7) byte aaah 555h aaah aaah 555h aaah note 9 word 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h es (10) erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bits until erase completes or erase is suspended another time. data 30h
11/33 m29w800at, M29W800AB table 10. status register bits note: logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. dq name logic level definition note 7 data polling '1' erase complete or erase block in erase suspend indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase on-going dq program complete or data of non erase block during erase suspend dq program on-going 6 toggle bit '-1-0-1-0-1-0-1-' erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete '-1-1-1-1-1-1-1-' erase complete or erase suspend on currently addressed block 5 error bit '1' program or erase error this bit is set to `1' in the case of programming or erase failure. '0' program or erase on-going 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). '0' erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c. 2 toggle bit '-1-0-1-0-1-0-1-' chip erase, erase or erase suspend on the currently addressed block. erase error due to the currently addressed block (when dq5 = `1'). indicates the erase status and allows to identify the erased block 1 program on-going, erase on- going on another block or erase complete dq erase suspend read on non erase suspend block 1 reserved 0 reserved
m29w800at, M29W800AB 12/33 during the second cycle the coded cycles consist of writing the data 55h at address 555h in the byte- wide configuration and at address 2aah in the word-wide configuration. in the byte-wide config- uration the address lines a1 to a10 are valid, in word-wide a0 to a11 are valid, other address lines are 'don't care'. the coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. instructions see table 9. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read opera- tions will read the memory array addressed and output the data read. a wait state of 10 m s is nec- essary after read/reset prior to any valid read if the memory was in an erase mode when the rd instruction is given. the read/reset command is not accepted during erase and erase suspend. auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address aaah in the byte-wide configuration or address 555h in the word-wide configuration for command set-up. a subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of a0 and a1. the manufacturer code, 20h, is output when the ad- dresses lines a0 and a1 are low, the device code, eeh for top boot, efh for bottom boot is output when a0 is high with a1 low. the as instruction also allows access to the block protection status. after giving the as instruction, a0 is set to v il with a1 at v ih , while a12-a18 de- fine the address of the block to be verified. a read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. program (pg) instruction. this instruction uses four write cycles. both for byte-wide configuration and for word-wide configuration. the program command a0h is written to address aaah in the byte-wide configuration or to address 555h in the word-wide configuration on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on the rising edge and starts the p/e.c. read operations output the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if pro- gramming is on-going and dq5 allows verification of any possible error. programming at an address not in blocks being erased is also possible during erase suspend. in this case, dq2 will toggle at the address being programmed. table 11. polling and toggle bits note: 1. toggle if the address is within a block being erased. '1' if the address is within a block not being erased. mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle note 1 erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle n/a toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. it can also be used to identify the block being erased. during erase or erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will set dq2 to '1' during erase and to dq2 during erase suspend. during chip erase a read operation will cause dq2 to toggle as all blocks are being erased. dq2 will be set to '1' dur- ing program operation and when erase is com- plete. after erase completion and if the error bit dq5 is set to '1', dq2 will toggle if the faulty block is addressed. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. in case of an error in block erase or program, the block in which the error oc- curred or to which the programmed data belongs, must be discarded. the dq5 failure condition will also appear if a user tries to program a '1' to a lo- cation that is previously programmed to '0'. other blocks may still be used. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0'. erase timer bit (dq3). this bit is set to '0' by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, after 50 m sto90 m s, dq3 returns to '1'. coded cycles the two coded cycles unlock the command inter- face. they are followed by an input command or a confirmation command. the coded cycles consist of writing the data aah at address aaah in the byte-wide configuration and at address 555h in the word-wide configuration during the first cycle.
13/33 m29w800at, M29W800AB figure 5. ac testing input output waveform ai01417 3v 0v 1.5v figure 6. ac testing load circuit ai01968 0.8v out c l = 30pf or 100pf c l includes jig capacitance 3.3k w 1n914 device under test table 13. capacitance (1) (t a =25 c, f = 1 mhz) note: sampled only, not 100% tested. table 14. dc characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v cc = 2.7v to 3.6v) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf symbol parameter test condition min typ. max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 supply current (read by word) e=v il ,g=v ih ,f=6mhz 310ma i cc2 supply current (read by word) e=v il ,g=v il , f = 6mhz 4.5 10 ma i cc3 supply current (stan-by) e = v cc 0.2v 30 100 m a i cc4 (1) supply current (program or erase) byte program, block or chip erase in progress 20 ma v il input low voltage 0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage cmos i oh = 100 m av cc 0.4v v v id a9 voltage (electronic signature) 11.5 12.5 v i id a9 current (electronic signature) a9 = v id 30 100 m a v lko (1) supply voltage (erase and program lock-out) 2.0 2.3 v table 12. ac measurement conditions input rise and fall times 10ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v
m29w800at, M29W800AB 14/33 table 15. read ac characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . 3. to be considered only if the reset pulse is given while the memory is in erase or program mode. symbol alt parameter test conditio n m29w800at / M29W800AB unit 80 90 v cc = 3.0v to 3.6v cl = 30pf v cc = 3.0v to 3.6v cl = 30pf min max min max t avav t rc address valid to next address valid e=v il, g=v il 80 90 ns t avqv t acc address valid to output valid e=v il, g=v il 80 90 ns t axqx t oh address transition to output transition e=v il, g=v il 00 ns t bhqv t fhqv byte switching high to output valid 50 50 ns t blqz t flqz byte switching low to output high z 50 50 ns t ehqx t oh chip enable high to output transition g=v il 00ns t ehqz (1) t hz chip enable high to output hi-z g=v il 30 30 ns t elbh t elbl t elfh t elfl chip enable to byte switching low or high 55ns t elqv (2) t ce chip enable low to output valid g=v il 80 90 ns t elqx (1) t lz chip enable low to output transition g=v il 00ns t ghqx t oh output enable high to output transition e=v il 00ns t ghqz (1) t df output enable high to output hi-z e=v il 30 30 ns t glqv (2) t oe output enable low to output valid e=v il 35 35 ns t glqx (1) t olz output enable low to output transition e=v il 00ns t phel t rh rp high to chip enable low 50 50 ns t plyh (1, 3) t rrb t ready rp low to read mode 10 10 m s t plpx t rp rp pulse width 500 500 ns
15/33 m29w800at, M29W800AB table 16. read ac characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . 3. to be considered only if the reset pulse is given while the memory is in erase or program mode. symbol alt parameter test conditio n m29w800at / M29W800AB unit 100 120 v cc = 2.7v to 3.6v cl = 30pf v cc = 2.7v to 3.6v cl = 30pf min max min max t avav t rc address valid to next address valid e=v il, g=v il 100 120 ns t avqv t acc address valid to output valid e=v il, g=v il 100 120 ns t axqx t oh address transition to output transition e=v il, g=v il 00 ns t bhqv t fhqv byte switching high to output valid 50 60 ns t blqz t flqz byte switching low to output high z 50 60 ns t ehqx t oh chip enable high to output transition g=v il 00ns t ehqz (1) t hz chip enable high to output hi-z g=v il 30 30 ns t elbh t elbl t elfh t elfl chip enable to byte switching low or high 55ns t elqv (2) t ce chip enable low to output valid g=v il 100 120 ns t elqx (1) t lz chip enable low to output transition g=v il 00ns t ghqx t oh output enable high to output transition e=v il 00ns t ghqz (1) t df output enable high to output hi-z e=v il 30 30 ns t glqv (2) t oe output enable low to output valid e=v il 40 50 ns t glqx (1) t olz output enable low to output transition e=v il 00ns t phel t rh rp high to chip enable low 50 50 ns t plyh (1, 3) t rrb t ready rp low to read mode 10 10 m s t plpx t rp rp pulse width 500 500 ns
m29w800at, M29W800AB 16/33 figure 7. read mode ac waveforms ai02182 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a18/ a1 e g dq0-dq7/ dq8-dq15 telqv valid address valid and chip enable output enable data valid byte tblqz telbl/telbh tehqz tghqz tbhqv note: write enable (w) = high.
17/33 m29w800at, M29W800AB table 17. write ac characteristics, w controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. sampled only, not 100% tested. 2. this timing is for temporary block unprotection operation. symbol alt parameter m29w800at / M29W800AB unit 80 90 v cc = 3.0v to 3.6v cl = 30pf v cc = 3.0v to 3.6v cl = 30pf min max min max t avav t wc address valid to next address valid 80 90 ns t avwl t as address valid to write enable low 0 0 ns t dvwh t ds input valid to write enable high 35 45 ns t elwl t cs chip enable low to write enable low 0 0 ns t ghwl output enable high to write enable low 0 0 ns t phphh (1, 2) t vidr rp rise time to v id 500 500 ns t phwl (1) t rsp rp high to write enable low 4 4 m s t plpx t rp rp pulse width 500 500 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl t oeh write enable high to output enable low 0 0 ns t whrl (1) t busy program erase valid to rb delay 90 90 ns t whwl t wph write enable high to write enable low 30 30 ns t wlax t ah write enable low to address transition 45 45 ns t wlwh t wp write enable low to write enable high 35 35 ns block erase (be) instruction. this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address aaah in the byte-wide configuration or address 555h in the word-wide configuration on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles. during the input of the second command an address within the block to be erased is given and latched into the memory. additional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further cod- ed cycles. the erase will start after the erase tim- eout period (see erase timer bit dq3 description). thus, additional erase confirm commands for oth- er blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is '0' the block erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase con- firm or if the coded cycles are wrong, the instruc- tion aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this automatically before to erasing to ffh. read operations after the sixth ris- ing edge of w or e output the status register status bits.
m29w800at, M29W800AB 18/33 table 18. write ac characteristics, w controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. sampled only, not 100% tested. 2. this timing is for temporary block unprotection operation. symbol alt parameter m29w800at / M29W800AB unit 100 120 v cc = 2.7v to 3.6v cl = 30pf v cc = 2.7v to 3.6v cl = 30pf min max min max t avav t wc address valid to next address valid 100 120 ns t avwl t as address valid to write enable low 0 0 ns t dvwh t ds input valid to write enable high 45 50 ns t elwl t cs chip enable low to write enable low 0 0 ns t ghwl output enable high to write enable low 0 0 ns t phphh (1, 2) t vidr rp rise time to v id 500 500 ns t phwl (1) t rsp rp high to write enable low 4 4 m s t plpx t rp rp pulse width 500 500 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl t oeh write enable high to output enable low 0 0 ns t whrl (1) t busy program erase valid to rb delay 90 90 ns t whwl t wph write enable high to write enable low 30 30 ns t wlax t ah write enable low to address transition 45 50 ns t wlwh t wp write enable low to write enable high 35 50 ns during the execution of the erase by the p/e.c., the memory accepts only the erase suspend es and read/reset rd instructions. data polling bit dq7 returns '0' while the erasure is in progress and '1' when it has completed. the toggle bit dq2 and dq6 toggle during the erase operation. they stop when erase is completed. after completion the status register bit dq5 returns '1' if there has been an erase failure. in such a situation, the tog- gle bit dq2 can be used to determine which block is not correctly erased. in the case of erase failure, a read/reset rd instruction is necessary in order to reset the p/e.c. chip erase (ce) instruction. this instruction uses six write cycles. the erase set-up command 80h is written to address aaah in the byte-wide configuration or the address 555h in the word- wide configuration on the third cycle after the two coded cycles. the chip erase confirm command 10h is similarly written on the sixth cycle after an- other two coded cycles. if the second command given is not an erase confirm or if the coded cy- cles are wrong, the instruction aborts and the de- vice is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing it to ffh. read operations after the sixth rising edge of w or e output the status register bits. during the exe- cution of the erase by the p/e.c., data polling bit dq7 returns '0', then '1' on completion. the toggle bits dq2 and dq6 toggle during erase operation and stop when erase is completed. after comple- tion the status register bit dq5 returns '1' if there has been an erase failure.
19/33 m29w800at, M29W800AB figure 8. write ac waveforms, w controlled note: address are latched on the falling edge of w, data is latched on the rising edge of w. ai02183 e g w a0-a18/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl erase suspend (es) instruction. the block erase operation may be suspended by this in- struction which consists of writing the command b0h without any specific address. no coded cy- cles are required. it permits reading of data from another block and programming in another block while an erase operation is in progress. erase sus- pend is accepted only during the block erase in- struction execution. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended. the toggle bits will stop toggling between 0.1 m s and 15 m s after the erase suspend (es) command has been written. the device will then automatically be set to read memory array mode. when erase is suspended, a read from blocks being erased will output dq2 toggling and dq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in both dq2 and dq6 toggling when the data is being programmed. a read/re- set command will definitively abort erasure and re- sult in invalid data in the blocks being erased. erase resume (er) instruction. if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles.
m29w800at, M29W800AB 20/33 table 19. write ac characteristics, e controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. sampled only, not 100% tested. 2. this timing is for temporary block unprotection operation. symbol alt parameter m29w800at / M29W800AB unit 80 90 v cc = 3.0v to 3.6v cl = 30pf v cc = 3.0v to 3.6v cl = 30pf min max min max t avav t wc address valid to next address valid 80 90 ns t avel t as address valid to chip enable low 0 0 ns t dveh t ds input valid to chip enable high 35 45 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehgl t oeh chip enable high to output enable low 0 0 ns t ehrl (1) t busy program erase valid to rb delay 80 90 ns t ehwh t wh chip enable high to write enable high 0 0 ns t elax t ah chip enable low to address transition 45 45 ns t eleh t cp chip enable low to chip enable high 35 35 ns t ghel output enable high chip enable low 0 0 ns t phphh (1, 2) t vidr rp rise time to v id 500 500 ns t phwl (1) t rsp rp high to write enable low 4 4 m s t plpx t rp rp pulse width 500 500 ns t vchwl t vcs v cc high to write enable low 50 50 m s t wlel t ws write enable low to chip enable low 0 0 ns power supply power up the memory command interface is reset on pow- er up to read array. the device does not accept commands on the first rising edge of w, if both w and e are at v il with g at v ih during power-up. any write cycle initiation is blocked when v cc is below v lko . supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v cc rail decoupled with a 0.1 m f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v cc pro- gram and erase currents required.
21/33 m29w800at, M29W800AB table 20. write ac characteristics, e controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. sampled only, not 100% tested. 2. this timing is for temporary block unprotection operation. symbol alt parameter m29w800at / M29W800AB unit 100 120 v cc = 2.7v to 3.6v cl = 30pf v cc = 2.7v to 3.6v cl = 30pf min max min max t avav t wc address valid to next address valid 100 120 ns t avel t as address valid to chip enable low 0 0 ns t dveh t ds input valid to chip enable high 45 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehgl t oeh chip enable high to output enable low 0 0 ns t ehrl (1) t busy program erase valid to rb delay 90 90 ns t ehwh t wh chip enable high to write enable high 0 0 ns t elax t ah chip enable low to address transition 45 50 ns t eleh t cp chip enable low to chip enable high 35 50 ns t ghel output enable high chip enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t phwl (1) t rsp rp high to write enable low 4 4 m s t plpx t rp rp pulse width 500 500 ns t vchwl t vcs v cc high to write enable low 50 50 m s t wlel t ws write enable low to chip enable low 0 0 ns
m29w800at, M29W800AB 22/33 figure 9. write ac waveforms, e controlled note: address are latched on the falling edge of e, data is latched on the rising edge of e. figure 10. read and write ac characteristics, rp related ai02184 e g w a0-a18/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl ai02091 rb w rp tplpx tphwl tplyh tphphh e tphel
23/33 m29w800at, M29W800AB table 21. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. all other timings are defined in read ac characteristics table. table 22. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) note: 1. all other timings are defined in read ac characteristics table. symbol parameter m29w800at / M29W800AB unit 80 90 v cc = 3.0v to 3.6v cl = 30pf v cc = 3.0v to 3.6v cl = 30pf min max min max t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 10 2400 m s chip enable high to dq7 valid (chip erase, e controlled) 1.0 60 1.0 60 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 m s chip enable high to output valid (chip erase) 1.0 60 1.0 60 sec t q7vqv q7 valid to output valid (data polling) 35 35 ns t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 ms write enable high to dq7 valid (chip erase, w controlled) 1.0 60 1.0 60 sec t whqv write enable high to output valid (program) 10 2400 10 2400 m s write enable high to output valid (chip erase) 1.0 60 1.0 60 sec symbol parameter m29w800at / M29W800AB unit 100 120 v cc = 2.7v to 3.6v cl = 30pf v cc = 2.7v to 3.6v cl = 30pf min max min max t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 10 2400 m s chip enable high to dq7 valid (chip erase, e controlled) 1.0 60 1.0 60 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 m s chip enable high to output valid (chip erase) 1.0 60 1.0 60 sec t q7vqv q7 valid to output valid (data polling) 40 50 ns t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 ms write enable high to dq7 valid (chip erase, w controlled) 1.0 60 1.0 60 sec t whqv write enable high to output valid (program) 10 2400 10 2400 m s write enable high to output valid (chip erase) 1.0 60 1.0 60 sec
m29w800at, M29W800AB 24/33 figure 11. data polling dq7 ac waveforms ai02185 e g w a0-a18/ a1 dq7 ignore valid dq0-dq6/ dq8-dq15 address (within blocks) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv
25/33 m29w800at, M29W800AB table 23. program, erase times and program, erase endurance cycles (t a = 0 to 70 c; v cc = 2.7v to 3.6v) note: 1. excluded the time required to execute bus cycles sequence for program operation. parameter m29w800at / M29W800AB unit min typ typical after (1) 100k w/e cycles max chip erase (preprogrammed, v cc = 2.7v) 10 10 sec chip erase (v cc = 2.7v) 15 15 sec main block erase (v cc = 2.7v) 1.5 15 sec chip program (byte) (1) 10 10 sec chip program (word) (1) 5 5 sec byte/word program 10 10 m s program/erase cycles (per block) 100,000 cycles figure 12. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 =1 dq7 = data yes no figure 13. data toggle flowchart read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 =1 no yes dq2, dq6 = toggle
m29w800at, M29W800AB 26/33 figure 14. data toggle dq6, dq2 ac waveforms ai02186 e g w a0-a18/ a1 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5,dq7/ dq8-dq15 note: all other timings are as a normal read cycle.
27/33 m29w800at, M29W800AB table 24. security block instruction note: 1. address bits a10-a19 are don't care for coded address inputs. 2. data bits dq8-dq15 are don't care for coded address inputs. mne. instr. cyc. unlock cycle 2nd cyc. 1st cyc. rds read security data 1 addr. (1) aah read otp data until a new write cycle is initiated. data (2) b8h figure 15. security block address table security memory block ai02746 top boot block 000ffh security memory block 00000h 0e0ffh 0e000h bottom boot block security memory block top boot block 0007fh security memory block 00000h 0e01fh 0e000h bottom boot block byte organisation (x8) word organisation (x16) security protection memory area the m29w800a features a security protection memory area. it consists of a memory block of 256 bytes or 128 words which is programmed in the st factory to store a unique code that uniquely identi- fies the part. this memory block can be read by using the read security data instruction (rds) as shown in table 24. read security data (rds) instruction. this rds uses a single write cycle instruction: the command b8h is written to the address aah. this sets the memory to the read security mode. any succes- sive read attempt will output the addressed secu- rity byte until a new write cycle is initiated.
m29w800at, M29W800AB 28/33 table 25. ordering information scheme devices are shipped from the factory with the memory content bits erased to '1'. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m29w800at 80 n 1 t device type m29 operating voltage w = 2.7 to 3.6v device function 800a = 8 mbit (1mb x8 or 512kb x16), boot block array matrix t = top boot b = bottom boot speed 80 = 80 ns 90 = 90 ns 100 = 100 ns 120 = 120 ns package n = tsop48: 12 x 20 mm m = so44 za = lfbga48: 0.8 mm pitch temperature range 1=0to70 c 5=20to85 c 6=40to85 c optio n t = tape & reel packing
29/33 m29w800at, M29W800AB table 26. revision history date description november 1998 first issue february 1999 removed tsop48 package reverse pinout march 1999 program, erase times and erase endurance cycles change 02/09/00 new document template document type: from preliminary data to data sheet program, erase times and endurance cycles change (table 23) lfbga package mechanical data change (table 29) lfbga package outline drawing change (figure 18) 03/06/00 program erase times change (table 23)
m29w800at, M29W800AB 30/33 table 27. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 0.0197 l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n48 48 cp 0.10 0.0039 figure 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
31/33 m29w800at, M29W800AB table 28. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data symbol mm inches typ min max typ min max a 2.42 2.62 0.0953 0.1031 a1 0.22 0.23 0.0087 0.0091 a2 2.25 2.35 0.0886 0.0925 b 0.50 0.0197 c 0.10 0.25 0.0039 0.0098 d 28.10 28.30 1.1063 1.1142 e 13.20 13.40 0.5197 0.5276 e 1.27 0.0500 h 15.90 16.10 0.6260 0.6339 l 0.80 0.0315 a 3 3 n44 44 cp 0.10 0.0039 figure 17. so44 - 44 lead plastic small outline, 525 mils body width, package outline drawing is not to scale. so-b e n cp b e a2 d c l a1 a h a 1
m29w800at, M29W800AB 32/33 figure 18. lfbga48 - 8 x 6 balls, 0.8 mm pitch, bottom view package outline drawing is not to scale. e1 e d1 d eb a2 a1 a bga-z00 ddd fd fe sd se ball oa1o table 29. lfbga48 - 8 x 6 balls, 0.8 mm pitch, package mechanical data symbol mm inch typ min max typ min max a 1.350 0.0531 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.750 1.000 0.0295 0.0394 b 0.300 0.550 0.0118 0.0217 d 9.000 8.800 9.200 0.3543 0.3465 0.3622 d1 5.600 0.2205 ddd 0.150 0.0059 e 0.800 0.0315 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 4.000 0.1575 fd 1.700 0.0669 fe 1.000 0.0394 sd 0.400 0.0157 se 0.400 0.0157
33/33 m29w800at, M29W800AB information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com

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